SESSION 1: Market Drivers and Supply Chain Collaboration

Session Leader: Dan Tracy, D.P. Tracy Associates

Heterogeneous Integration will deliver increase system functionality in a small footprint, and to achieve such solutions will require collaboration along the electronic industry’s supply chain to solve and address the challenges. This session will provide a perspective of the challenges for supply chain participants in terms of collaboration; highlight market drivers and the opportunities for collaboration; and identify how business models will adapt, change, and evolve to deliver solutions needed to achieve Heterogeneous Integration. Effective collaboration, aligned with the market needs, will enable our industry to deliver cost-effective and reliable solutions for Heterogeneous Integration.

Keynote Speaker:
Heterogeneous Integration: Is it Ready for Changing the Packaging Landscape?
Risto Puhakken, President, VLSI

IC manufacturing will change as the node transitions slow and classic shrinking becomes more difficult and expensive. Heterogeneous Integration is often claimed to be the cure for these challenges. However, is it ready for the prime time?

The presentation takes a long view on the packaging interconnect technologies and explores under what conditions Heterogeneous Integration is able to create substantial change in the IC packaging landscape. This is a prerequisite to achieve reasonable market share among interconnect technologies and creating fundamental change in the IC packaging business.

Cost Effective Solutions for System Integration
Dr. Dongkai Shangguan, Vice President for Advanced Manufacturing Engineering, Flex

Abstract To Follow

SESSION 2: Design and Test of Chiplets and Multi-die ICs

Session Leader: Herb Reiter, eda 2 asic Consulting, Inc.

Integrating heterogeneous functions - as "Chiplets" - into advanced IC packages offers lots of flexibility, saves space and increases performance per Watt. However, multi-die ICs demand closer cooperation and more bi-directional data to flow across the supply chain, to get to revenue faster, reduce unit cost and risk.

In this session experts from across the multi-die EcoSystem will outline common challenges as well as explain proven solutions and ongoing enhancement efforts. In addition, executives from the Electronic System Design Alliance (representing EDA, IC and system design firms) and from SEMI (representing IC manufacturing & test companies and their suppliers) will outline why they recently formed a Strategic Alliance and describe how they'll contribute to significantly closer cooperation across the entire supply chain.

Keynote Speaker:
Disruption is Coming: Adapt, Change or Be Left Behind
Keith Felton, Product Marketing – IC Packaging, Mentor Graphics Board Systems Division

New, emerging and existing markets demand ever-smaller electronic devices that surpass the performance of their physically larger predecessors with thinner and smaller form factors, lighter, increased functionality with faster data transfer, and without sacrificing battery lifetime and affordability. Enter a new breed of packaging that we term as High Density Advanced Packaging (HDAP) it’s the evolutionary offspring of its silicon foundry and organic package OSAT parents, where genes of both are mixed and result in something that can be highly disruptive. These next generation packages can come in different forms, the most well-known is FOWLP, that itself has multiple flavors, InFO from TSMC which was made famous by Apple, SWIFT from Amkor, M-series from DECA and there are others. Even within FOWLP there are many varieties. Of course there are other new integration platforms such as silicon interposers, sometimes call 2.5D which can be mixed with FOWLP or with an organic BGA package or even both. Implementing this new generation of packages requires a significant expansion in the communication between the IC design world the package design world plus a new dimension, that of communication and interaction with the OSAT/Foundry that will fabricate and assemble the complete device. This presentation will explore best practice approaches for embarking into HDAP design, how to leverage your Foundry or Outsourced Substrate Assembly and Test (OSAT) partner, how to ensure your design is manufacturable first time, avoiding expensive and time consuming changes or redesign.

Design and Manufacturing – From Silos to Strategic Collaboration
Bob Smith, Executive Director, ESD Alliance (a SEMI Strategic Association Partner)
Bettina Weiss, Vice President Business Development, SEMI

Applications for semiconductor technology have moved from monolithic (computing, mobile and networking/communications) to wide ranging (IOT, autonomous driving, AI) devices, bringing with them innovative new applications that were virtually unknown just 5 years ago. At the same time, the semiconductor and adjacent industries have experienced unprecedented consolidation, significantly changing supply chain dynamics and opening the door for new, often big, players. This presentation addresses, from the vantage point of a global industry association, how not-for-profit, member-driven organizations need to partner smartly and provide their members opportunities to connect, collaborate and innovate together. The presentation will focus particularly on the integration of the ESD Alliance as a SEMI Strategic Association Partner and the opportunities that their members can now realize when connecting the vibrant electronic system design and IP community with global platforms – where 1+1 >2.

As the Industry Starts to Look Away from SOC and Towards Heterogeneous Integration, What New Challenges are Emerging for Design and Test?
John Park, Product Management Director, IC Packaging and Cross-Platform Solutions, Cadence Design Systems
Lisa Jensen, Product Engineering Director, Modus DFT Software Solutions, Cadence Design Systems

Gordon Moore predicted a trajectory in which the transistor count of IC’s would double every two years driving transistor cost on a constant downward path. This prediction later came to be known as Moore’s Law. For the past several decades, the electronics industry has thrived while enjoying the benefits of Moore’s Law. It’s been a great run. However, the new semiconductor growth engines like HPC and AI are forcing engineers to consider design alternatives to SOC. In many cases, they are looking at advanced, multi-chip(let)/system in a package (heterogeneous integration) technologies to not only solve the next generation of design challenges, but also keep costs in check. This presentation will provide an overview of the latest trends in heterogeneous integration and describe some of the design/test challenges that will need to be addressed to support the next generation of multi-chip(let) designs.

SESSION 3: The Manufacturing Challenges of Heterogeneous Packaging

Session Leader: Joel Camarda, Altierre

The complex heterogeneous SIP (system in package) may contain a mix of interconnection technologies and materials.  The interconnect may be wire bonding (gold, copper, aluminum) ,  flip chip (solder  bump, copper pillar, micropillar), TSV,  sputtered meatal, fusion bonding, and/or  combinations thereof in the same package.  Wafer fab manufacturing technologies have migrated into the package.  Substrates and interposers may include lead frames, patterned silicon, glass, or organic.  Die stacking is becoming widespread, performed at wafer level or single chip to single chip.  This manufacturing session will feature technical experts from prominent equipment and material suppliers and OSATs discussing their leading edge capabilities currently in production and their assessment of their next challenges.

Keynote Speaker:
Heterogeneous Integration Roadmap and SiP
William “Bill” Chen, ASE Fellow and Senior Technical Advisor, ASE Group

Abstract To Follow

Interconnection Technologies Critical to 2.5D and 3D Heterogeneous Integration
Bob Chylak, Vice President Process R&D, Kulicke & Soffa

Abstract To Follow

Presentation Title - To Be Announced
Tim Olson, Founder, CTO and board member, Deca Technologies

Abstract To Follow

SESSION 1: Market Drivers and Supply Chain Collaboration
SESSION 2: Design and Test of Chiplets and Multi-die ICs
SESSION 3: The Manufacturing Challenges of Heterogeneous Packaging
SESSION 4: PANEL: Supply Chain Issues for Advanced Packaging

SESSION 4: Panel Discussion: Supply Chain Issues for Advanced Packaging

Moderator: Ed Sperling, founder and Editor-in-Chief, Semiconductor Engineering Magazine

The slowdown in Moore's Law has forced companies to rethink architectures and IP and how to integrate everything together, but realigning the supply chain around a long list of packaging options is a huge undertaking. It requires a secure marketplace, varying levels of characterization, and support from foundries and OSATs. And it requires the industry to commit to standards and processes that so far don't exist in order to maximize yield and reduce unexpected interactions, potential security issues and improved performance with lower power at a reasonable cost.

Panelists To Be Announced