MEPTEC (MicroElectronics Packaging and Test Engineering Council) is a trade association of semiconductor suppliers, manufacturers, and vendors concerned exclusively with packaging, assembly, and test. Since its inception over 30 years ago, MEPTEC has provided a forum for semiconductor packaging and test professionals to learn and exchange ideas that relate to packaging, assembly, and test. Through our monthly luncheons, symposiums, and an Advisory Board consisting of individuals from all segments of the semiconductor industry, MEPTEC continuously strives to improve and elevate the roles of assembly and test professionals in the industry.
Wednesday, February 5, 2020 / 11:30 am — 1:00 pm
SEMI Global Headquarters
673 South Milpitas Blvd
Milpitas, CA 95035
Next Generation 2.5D/3D Packaging Architecture
in Data Center Applications
Dr. Preeti S. Chauhan, Technical Program Manager
Data Center Quality, Google
With the growing demand of increased computing performance and increase bandwidth, innovative 2.5D/3D packaging technologies are continually being developed. The die to die stacking technology enables the integration of logic dies with multiple technology nodes, as well as logic to memory dies. The resulting architecture has potential applications in the data center machines where this heterogeneous integration enables high compute power, increased memory bandwidth and reduced power consumption. This presentation will cover some of the 2.5D/3D integration technologies for data center applications along with the associated challenges and growth opportunities.