Test Challenges for Heterogeneous Device Integration
As devices become more and more complex the challenges to test them are growing significantly. At the same time that individual devices are becoming more complex, thanks to smaller geometries, the spectrum of device types is growing thanks to heterogenous integration techniques. This presentation will summarize the roadmap conclusions and predictions of the 2017 Test Working Group highlighting key areas of near and long-term concern as well as strategies and technologies which will become critical as we move forward.
A Revolution in Systems Integration as CMOS Scaling Slows
The benefits of Moore’s Law scaling have been decreasing for almost a decade and yet the pace of progress is accelerating. The issues that define progress for information technology are size, weight, latency, power requirement, thermal management, bandwidth density and cost, all at the product level. Acceleration of progress in all of these parameters comes even as the “tail wind” from scaling CMOS is making a decreasing contribution.
The development of a full eco-system to support this revolution has occurred over the past decade with innovations such as fan-out wafer level packaging, 2.5D and 3D integration, through silicon vias, new materials, etc. The co-design and simulation tools supporting the short product life cycles of consumer dominated markets are emerging.
Heterogeneous Integration is the enabling architecture supporting this accelerated pace of progress. New materials, processes and architectures are emerging and the early adopters are realizing economic success using these leading-edge technologies. The wave of “fast followers” is rising as many companies are in development with complex-3DTSV System in Package products. Yields are improving and costs are coming down. CMOS logic and memory co-exist with photonics, MEMS, integrated passive devices, integrated power devices and a steady flow of new device types.
There is much that remains to be done and it will be accelerated if a mechanism exists to identify opportunities for pre-competitive collaboration in this new eco system of heterogeneous integration. This need was anticipated and, beginning in early 2015, the Heterogeneous Integration Roadmap had its beginning with an MOU between the newly formed ITRS Heterogeneous Focus Team and the IEEE Electronic Packaging Society. Today this activity has grown with 5 institutional sponsors, 21 working groups and almost 1,000 participants in the face to face meetings held around the world in 2016. The elements of this revolution and some projections of the results we can expect over the next 15 years will be discussed.
Heterogenous Integration – a Systems-level Reliability Perspective
This presentation will focus on the approach and essentials of integrating a heterogenous package at a Device or Systems-level with a design-for-reliability framework in mind. Approach is rooted in a Physics-of-Failure approach at the package and device level. Examples are provided to illustrate the approach and challenges current and future are discussed.
Can the Packaging Community Establish a Real Design for Heterogeneous Integration Ecosystem?
The next generation system-in-package (SiP) will involve complex, multi-die heterogeneous integration. The key to rapid time to market is an alignment and early handshake on all aspects of design, manufacturing and reliability. Since the various dice and other components (including embedded components) are expected to come from diverse foundries and encompass widely varying technology nodes, integration of design and simulation tools is a key aspect. Co-design will require not just to be a “buzzword”, but to become an essential element in the toolkit for an effective system design and hand-off to manufacturing and assembly. The panelists will discuss the essential elements for making this a success.
Should We Rethink the Reliability Standards for these Heterogeneous Integrated SIP Packages?
Current JEDEC standards, developed decades ago in many cases, are largely driven by requirements of military grade applications. Today’s Internet of Everything (IoE) with connected world devices are much more consumer based with a different and typically relaxed set of end use reliability requirements. On the other hand, emerging trends in automotive and high frequency communication may require “zero-defect” based criteria. Therefore, end-user based quality and reliability specifications are key for rapid adoption of new technologies. The panelists will discuss the desirability and viability of revising the current reliability specifications for these devices.
What are the Best Test Strategies and Guiding Principles for these Heterogeneous Integrations?
Heterogeneous integration technology combines multiple functional IC’s and passives into a single package which requires complete SIP test. The primary objective of the SIP Test is to verify the connectivity of components in the module as well as perform a basic functional quality check of IC’s and passives on board. SIP test strategies are driven by feasibility of using existing low cost automated test equipment (ATE) or designing very low cost custom System Level Testers (SLT) with the ultimate goal of minimizing the cost of test and lead time to production. The panelists will review the challenges (Technology, Cost and Lead Time) to launch high volume manufacturing (HVM) by using ATE equipment that can be reusable for multiple products vs SLT that needs to be designed per SIP.