In this post ITRS era, there is great need for the industry to collaborate in charting a direction into the future. In 2015, the SIA announced their decision to bring ITRS to a close, with the 2015 edition being the final edition. The IEEE CPMT Society took the initiative to establish a technology roadmap focused on heterogeneous integration, to be modeled after the ITRS in purpose, structure, and governance. This initiative quickly found resonance with SEMI, and the IEEE Electron Devices Society (EDS) joined the effort, resulting in the launch of the Heterogeneous Integration Roadmap (HIR). MEPTEC has moved to participate in this roadmap collaboration.
MORNING SESSION: Strategic Directions in Heterogeneous Integration
The morning session will address the strategic directions in heterogeneous integration that address the market inflection points and technology fault lines. What will be the crucial roles for integrated phonics for data to the cloud, and for sensing? What technologies will be developed and implemented for the self driven cars be introduced into our cities and byways? How embedded sensing will enable the transition from IoT to IoE around the world.
AFTERNOON SESSION: Innovations in SiP and Integration
This session will address the major developments in heterogeneous components – power devices, analog, MEMS sensors, photonics, and in SiP integration – fan out, 2.5D, embedded, and co-design technologies. How will the momentum of these technology developments move forward to address road blocks moving ahead? What research areas and ecosystem collaboration will be needed for continued progress? These and more questions will be addressed.
PANEL DISCUSSION: Packaging Solutions to Meet Needs of the Heterogeneous Integration Roadmap
Heterogeneous integration technology is critically important to deliver the performance and functionality for both autonomous computing and a world of connected devices. The HIR is a pre-competitive technology roadmap that provides long term vision into the future to identify the technologies at the semiconductor, package, and system integration level that will address future technology requirements. The panel will review future challenges in areas such as data rate, thermal performance, miniaturization and interconnect density, and discuss emerging solutions for these challenges.