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Introduction
Packaging technology continues to drive
Thursday, October 23, 2014

In the areas of both design and manufacturing, the industry is pushing the limits, even in technologies once thought to be mature. Wafer bumping, wire bonding, and surface mount technology, for example, are all very active topics in the research labs and manufacturing lines. On the design side, work continues in areas like system partitioning, materials, and design tool development. With all of this progress, the bridge that spans them – design for manufacturability (DFM) – has become more important than ever.

This year, for its annual industry update, MEPTEC is bringing together packaging experts in these critical areas and others to present detailed technical updates. Don’t miss your chance to get up to speed on today’s most important topics in packaging, all in one place on one day. The opportunity to learn is enhanced with MEPTEC’s unmatched Silicon Valley networking opportunities built into the day.

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Pushing the Limits in Packaging

Wafer Fab, Packaging, and Test – Supply Chain Coordination as a Critical Capability
Session Leader: Phil Marcoux, FOA

Wafer fabs are expecting more from their package and test resources. IC packaging is continuing to be complicated, capital intensive, and unpredictable.  The number of different package types marketed in the last ten years exceeds the number of different types deployed in the entire prior forty years of the semiconductor industry.

Due to pressures from the wafer device makers, semiconductor packaging is taking on features similar to the more capital intensive front-end wafer processing.  This results in common challenges (and opportunities) for the entire semiconductor wafer, packaging, and test supply chain. The speakers in this session will help sort out the issues and suggest solutions where they can.

Enabling Multi-Die Packaging as a Mainstream Solution
Session Leader: Jeff Demmin, STATSChipPAC

Integration of more than one semiconductor device in a single package is nothing new.  What used to be just a high-end approach, though – picture multi-chip modules from 20 years ago – is now a common solution in many applications from consumer electronics to servers.  This range of applications creates a variety of challenges in design and manufacturing, including wafer thinning, stacking, interconnect, thermal management, and reliability. 

This session will report on the latest technical developments that enable such configurations as processor / memory integration in mobile products, stacked memory, and RF modules.

Pushing the Envelope on IC Package Manufacturing
Session Leader: Joel Camarda, SemiOps

This session will concentrate on leading-edge process technologies -- the non-proprietary capabilities and associated the process, equipment, and material details.

Wire bonding is declared to be obsolete at least every 10 years (via TAB, flip chip, wafer-level packaging, etc.), but it still remains the dominant interconnect. Beyond conventional gold and aluminum wire, we have seen copper wire, silver wire, insulated wire, longer wires, thinner wires, finer pitch bonding, multi-level bonding, and so on. How is this accomplished? Die bumping has also progressed consistently for many years with greater densities and process improvements. Solder bumps have yielded to finer pitched copper columns for many applications. What have been the key process enablers, and where is it headed? Substrate line, pitch, and via densities have also continued to advance. What are the key process enablers in materials and equipment?

Design Considerations for Advanced Package Development
Session Leader: John Xie, Altera

With the increased complexity of silicon in advanced process nodes, it is becoming more difficult to meet density, performance, and cost targets simultaneously. Optimizing the chip / package interface using the IC-PKG co-design concept is one of the critical processes in achieving product objectives. Meanwhile, IC-PKG co-design has also expanded beyond the chip / package interface -- it goes deeper into silicon layers and extends to the PCB and system. This industry-wide trend puts a high demand on EDA tools and features, new design flows, new concepts in product architectures, and the knowledge and skills of designers of ICs, packages, and PCBs. This session will include speakers who will discuss the latest developments in design from the EDA community, IC companies, and the packaging industry.

Ivor Barber, Xilinx
• Joel Camarda, SemiOps
• Jeff Demmin, STATS ChipPAC
• Nikhil Kelkar, Exar Corporation
• Phil Marcoux, FOA
• Rich Rice, ASE (U.S.) Inc.
• Jim Walker, Gartner
John Xie, Altera Corp.

Exhibit spaces are limited. Exhibit fee include:

• 6’ table, draped
• 2 chairs
•11”x17” custom table top sign with your logo and company Ndescription
One admission to the conference
Logo on event home page
• Logo, link to your URL and company description on special
NExhibitor web page
• Company description in the symposium proceedings
• Printed and electronics versions of the symposium proceedings
• Marketing exposure through e-mail campaign

Click here for pricing and to reserve a table now. For more information contact Bette Cooper at bcooper@meptec.org
or call 650-714-1570.

Sponsoring this event will provide a valuable opportunity to promote your company brand and product/service message to attendees, while supporting your business development and positioning goals. For benefits and pricing click on the Sponsorship Benefits link below. Click on the Sponsorship Application Form link below. For more information contact Bette Cooper at bcooper@meptec.org or call 650-714-1570.

Cost of admission includes attendance, continental breakfast, refreshment breaks, lunch, and printed and online proceedings. A credit card is needed to hold the reservation.

Pre-registration is strongly recommended. There will be no guarantee of space or materials for on-site registrants.

Final confirmation including maps and directions will be sent by October 20.

Refunds for advance payment, less a $50 processing fee, will be given in full provided cancellation by phone or e-mail is received 10 business days before the event (Thursday, May 8). If you do not cancel by May 8 or are a no-show, the credit card provided to hold the reservation will be charged for the full amount.

MEPTEC has secured a special rate at the Biltmore Hotel of $199.00 from October 21 - October 23. Call 408-988-8411 or 800-255-9925 to reserve your room. Be sure to mention MEPTEC in order to secure your special rate.